Signal-limiting amplifiers



April 1965 G. c. LOCKWOOD 3,179,819

SIGNAL-LIMITING AMPLIFIERS Original Filed Jan. 19, 1961 2 Sheets-Sheet 1FIG. I (I4 :5 I3 l27| f SIGNAL INPUT FIG. 2

I5 I22 |2 l SIGNAL INPUT INVENTOR GEORGE C. LOCKWOOD HIS ATTORNEYS April20, 1965 G. C. LOCKWOOD Original Filed Jan. 19 1961 S IGNAL-LIMITINGAMPLIFIERS V '7. 2 Sheets-Sheet 2 RIG. 3

l5 3 I21 SIGNAL 1 INPUT H I9 23 22 3f +v 24 I6 FIG. 4

l3 l2 l0 3: SIGNAL INPUT 7 INVENTOR GEORGE C. LOCKWOOD BY am HISATTORNEYS United States Patent 3 tllaims. (Cl. 307-885) This applicationis a continuation of application Serial No. 83,703 of George C. Lockwoodfor Signal Amplifying System, filed January 19, 1961, now abandoned.

The present invention relates generally to a new and improvedsignal-translating apparatus and more specifically relates to a novellimiting amplifier capable of bilaterally limiting the amplitude of aninput signal.

In substantially all of the various well-known limiting amplifiers,signal limiting is normally accomplished in a manner whereby signalexcursions of one polarity cause the particular translating device beingutilized to be biased to cut-off, whereas signal excursions of theopposite polarity bias the translating device to saturation. In the typeof limiting amplifier in which a transistor is utilized as thesignal-translating device, the input impedance thereof drops essentiallyto zero each time the transistor is driven to saturation. Such acharacteristic is highly undesirable in those circuits having animpedance matching requirement. In addition, it is a well-knownphenomenon that, after a transistor is driven to saturation, a definiteamount of delay is encountered in subsequently turning the transistorofi, due to the fact that the minority carriers must be removed from thebase before collector current ceases to flow. In present-day high-speedcomputing devices, this delay is at times appreciable with respect tothe total computing time involved and, accordingly, is constantly soughtto be eliminated.

It is a primary object of the present invention to devise a new andimproved signal-translating apparatus which is of comparatively simplecircuit arrangement and yet is highly efiective in bilaterally limitingthe amplitude of an incoming signal. 7

A more specific object of the present invention is to devise a novellimiting amplifier circuit which does not depend upon saturation of theparticular signal-translat ing device utilized, is extremelyfast-acting, and maintains a substantially constant input impedanceduring operation thereof.

. In accordance with the present invention, such a novel signal-limitingamplifier circuit comprises a signal translating device having an inputelectrode, an output electrode, and a common electrode. A first seriescircuit arrangement comprising a relatively low value degenerationresistor connected to said common electrode of said translating deviceand a relatively high value biasingdegeneration resistor connected to asource of biasing potential is provided for forward biasing thetranslating device such that a steady state bias current normally flowstherethrough of a predetermined threshold level with the result that asignal applied to the input electrode of the translatingdevice causesamplitude variations of the current therethrough about the thusestablished bias level. The limiting amplifier further includes a secondseries circuit arrangement comprising a capacitive device connected tothe junction of the degeneration resistors and a unilaterallyconductingdevice connected to a source of reference potential, and means forforward biasing the unilaterally conducting device so that a steadystate bias current normally flows therethrough of a magnitudesubstantially equal to the magnitude of the maximum desired currentvariation through the translating device above the threshold level,whereby any small-amplitude input sig- 3 ,1 79,8 l 9 Patented Apr. 20,1965 nal components which cause amplitude variations of the currentthrough the translating device below the maximum desired value aresubstantially amplified and any largeamplitude input signal componentswhich tend to cause amplitude variations of the current through thetranslating device above the maximum desired value causes theunilaterally conducting device to be cut-off and thereby renders thebiasing-degeneration resistor operative to elfect a substantialattenuation of the large-amplitude signal components.

The features of the present invention which are believed to be novel areset forth with particularity in the appended claims. The organizationand manner of operation of the invention, together with further objectsand advantages thereof, may best be understood by reference to thefollowing description, taken in connection with the accompanyingdrawings, in the several figures of which, like reference numeralsidentify like or similar elements, and in which:

FIG. 1 is a schematic illustration depicting the novel features of thepresent invention; and

FIGS. 2 through 4 schematically illustrate various other embodiments ofthe present invention.

With reference to FIG. 1, a limiting amplifier circuit constructed inaccordance with the present. invention preferably comprises asignal-translating device in the form of a PNP junction transistor 10,the base of which functions as an input electrode, the collector ofwhich functions asan output electrode, and the emitter of whichfunctions as a common electrode. Accordingly, the base of the transistoris returned through resistor 11 to a suitable source of referencepotential such as ground and is additionally coupled through couplingcapacitor 12 to input terminal 13, which is adapted to receive analternating polarity signal from any suitable source such as, forexample, those shown and described in section 14 of the Handbook ofSemi-Conductor Electronics, by L. P. Hunter. The transistor collector iscoupled through con pling capacitor 14 to load 15 and, additionally, isconnected through dropping resistor 16 to bias terminal 17, which, inturn, is adapted to be connected to a suitable source of negativeunidirectional operating potential. The transistor emitter is connectedto a suitable source of reference potential, such. as ground, through aseries circuit arrangement comprising degeneration resistor 18, couplingcapacitor 19, and crystal diode 20. The junctions between resistor 18and capacitor 19 and between capacitor 19 and crystal diode 20 arerespectively connected through dropping resistors 21 and 22 to biasterminal 23, which is adapted to be connected to a suitable source ofpositive unidirectional operating potential.

The mode of operation of the circuit arrangement illustrated in FIG. 1is as follows: Due to the fact that the base of the transistor isreturned to ground potential via resistor 11 and the common electrodethereof-Le, the emitter-is coupled to a positive bias source viaterminal 23 and series-connected resistors 18 and 21, the emitterbasejunction of the transistor is forward biased in the low resistancedirection; consequently base current flows outwardly therefrom andthereby renders the transistor normally conductive. The value ofdropping resistor 21 is chosen to be several orders of magnitude greaterthan the value of the dynamic base-to-emitter resistance of thetransistor plus the value of degeneration resistor 18, so that,neglecting the negligible potential drop across resistor 11 due to basecurrent flowing therethrough, a close approximation of value of thesteady state emitter current flowing into the transistor is determinedby dividing the magnitude of the bias potential applied to terminal 23by the value of resistor 21..

It is also to be noted that diode 20 is forward biased by an amountdetermined by the value of dropping resis- 3 tor 22 and the magnitude ofthe bias potential applied to bias terminal 23. Consequently, diode 20is normally rendered conductive, whereby its impedance in the forwarddirection is substantially zero. For reasons to become more apparenthereinafter, it is preferred that the values of bias resistors 21 and 22be equal, so that the biascurrent flowing into the transistor issubstantially equal to the bias current flowing through diode 20. Thevalues of coupling and bypass capacitors 12, 14, and 19 are desired tobe sufficiently high to provide low impedance signal paths at thefrequency of the input signal which is applied to the base of thetransistor via input terminal 13. Thus, by virtue of the fact that areplica of the input signal applied to the base of the transistorappears on its emitter (neglecting the negligible potential drop acrossthe dynamic base-to-emitter impedance of the transistor), theinstantaneous value of the signal current flowing through the seriescircuit arrangement comprising diode 20, capacitor 19, and resistor 18is substantially equal to the instantaneous value of the input signalpotential, hereinafter designated E, divided by the value ofdegeneration resistor 18, hereinafter designated R Stated another way,the degree or amount by which the input signal modulates the steadystate emitter current is efiectively determined by the quotient E/ RTherefore, when the instantaneous amplitude of the input signalpotential is positive by an amount such that the quotient E/R is equalto or greater than the value of the steady state emitter current, thenet emitter current flowing into the transistor is substantially reducedto zero,

resulting in the transistors being cut off. However, prior to the timethe transistor is cut off, the circuit has maximum gain characteristicwith respect to the incoming signal, during which time the instantaneousvalue of the current flowing through diode 20 is substantially equal tothe algebraic summation of the steady state bias current and thealternating signal current flowing therethrough. As previously stated,the magnitude of the steady state bias current'through diode 20 issubstantially determined by the value of resistor 22 and the magnitudeof the bias potential at terminal 23, whereas the instantaneous value ofthe signal current therethrough is substantially determined by the valueof resistor 18 and the instantaneous value of the signal potentialapplied to input terminal 13. Thus, when the instantaneous amplitude ofthe input signal is increased negatively, the emitter current isproportionally increased, so that, when the instantaneous amplitude ofthe input signal potential is negative by an amount such that thequotient E/R is equal to the value of the steady state emitter current,the total instantaneous emitter current flowing into the transistor istwice the value of the steady state emitter current.

When the instantaneous magnitude of the input signal increasesnegatively until the instantaneous emitter current is twice the steadystate value, the current through diode 20 is reduced substantially tozero.

As a result of the current through diode 24} being reduced to zero, theparallel combination of resistors 21 and 22 is operatively connected inseries with resistor 18 to provide a substantial increase indegeneration in the transistor, so

that a further increase of the input signal in a negative direction doesnot appreciably cause a further increase in emitter current.

Thus, there has been devised a novel signal amplifier and limiter whichdoes not depend upon transistor saturation. As a result of the absenceof saturation, substantially constant input impedance is maintained,and, in addition, the circuit is extremely fast acting and maintains asubstantially constant limiting level.

In order to attain symmetrical limiting, it is necessary for the steadystate bias current through diode 20 to be substantially equal inmagnitude to the steady state bias current flowing into the emitter ofthe transistor. However, whether or not symmetrical limiting is desired,it is to be appreciated that diode 20 is forward biased by an Transistor10- Terininal 1710 v. Resistor 22-10 KS2.

ZN iOiGT.

Resistor 11- Resistor 18-200S2. Terminal 23+10 v.

Capacitor 12 p Capacitor 14- 1 pf. Resistor lG-4 KS2.

Capacitor 191 ,uf.

Diode 20-1 N34.

Resistor 2l-10 KS2.

Limiting level- :l=.2 v.

While a particular embdiment of the invention has been shown anddescribed with respect to FIG. 1, from a comprehension of the foregoingit will be readily obvious to those skilled in the art that changes andmodifications may be made without departing from the invention in itsbroader aspects. For example, while a PNP junction transistor isillustrated as a'rnatter of convenience, it is immediately obvious thatan NPN transistor may equally Well be employed, providing thatthe'various bias and operating voltages of the circuit are appropriatelychanged in a manner well known to those skilled in the art. A furtherobvious modification may be made in the manner illustrated in FIG. 2. Inthis embodiment, transistor 10 is replaced by a conventional vacuum tubesimply by suitably reversing the polarity of diode 20 and the polaritiesof the bias potentials at terminals 17 and 23. The modificationillustratedin FIG. 3 involves returning resistor 21 to ground ratherthan to terminal 23, plus the addition of resistor 24 connected betweenthe base of transistor 10 and bias terminal 17. In the mannerillustrated in FIG. 4, the circuit arrangement of FIG. 3 maysuccessfully be further modified by returning resistor 22 to groundrather than to bias terminal 23, plus returning the cathode of diode 2t)to a source of negative potential via terminal 25 rather than to groundas in FIG. 3.. As the mode of operation of each of the modified circuitarrangements illustrated in FIGS. 2 through 4 is practically identicalwith respect to the mode of operation of the circuit arrangement of FIG.1, which has hereinbefore been fully described in detail, a furtherdetailed description thereof is not deemed necessary.

Having thus fully described the various novel aspects of the presentinvention together with various changes and modifications thereof, theaim in the appended claims is to cover all such changes andmodifications as fall within the true spirit and scope of the invention.

Whatis claimed is: V

1. A signal-limiting amplifier circuit comprising:

a transistor having an input electrode, an output electrode, and acommon electrode;

a first series circuit means comprising a relatively low valuedegeneration resistor connected to said common electrode of saidtransistor and a relatively high value biasing-degeneration resistorconnected to a source of biasing potential for forward biasing saidtransistor such that a steady state bias current normally flowstherethrough of a predetermined threshold level with the result that asignal applied to said input electrode causes amplitude variations ofsaid current about said bias level;

a second series circuit arrangement comprising a capacitive deviceconnected to the junction of said de-' tion of said capacitive deviceand said unilaterally conducting device for forward biasing saidunilaterally conducting device with a steady state bias current of amagnitude substantially equal to the magmaximum value cause saidunilaterally conducting device to be cut-off thereby rendering saidbiasingdegeneration resistor operative to eifect attenuation of saidlarge amplitude signal components.

nitude of maximum desired current variation through 5 2. Asignal-limiting amplifier circuit in accordance with said transistorabove said threshold level, whereby claim 1 wherein the emitterelectrode of said transistor any small amplitude input signal componentscausing constitutes the common electrode.

amplitude variations of the current through s id 3. A signal-limitingamplifier cirouitin accordance with transistor below the desired maximumvalue are am.- claim 1 wherein said transistor is of a variety. plifiedand any large amplitude input signal com- 10 ponents tending to causeamplitude variations of the current through said transistor above thesaid desired No references cited.

JOHN W. HUCKERT, Primary Examiner.

1. A SIGNAL-LIMITING AMPLIFIER CIRCUIT COMPRISING: A TRANSISTOR HAVINGAN INPUT ELECTRODE, AN OUTPUT ELECTRODE, AND A COMMON ELECTRODE; A FIRSTSERIES CIRCUIT MEANS COMPRISING A RELATIVELY LOW VALUE DEGENERATIONRESISTOR CONNECTED TO SAID COMMON ELECTRODE OF SAID TRANSISTOR AND ARELATIVELY HIGH VALUE BIASING-DEGENERATION RESISTOR CONNECTED TO ASOURCE OF BIASING POTENTIAL FOR FORWARD BIASING SAID TRANSISTOR SUCHTHAT A STEADY STATE BIAS CURRENT NORMALLY FLOWS THERETHROUGH OF APREDETERMINED THRESHOLD LEVEL WITH THE RESULT THAT A SIGNAL APPLIED TOSAID INPUT ELECTRODE CAUSES AMPLITUDE VARIATIONS OF SAID CURRENT ABOUTSAID BIAS LEVEL; A SECOND SERIES CIRCUIT ARRANGEMENT COMPRISING ACAPACITIVE DEVICE CONNECTED TO THE JUNCTION OF SAID DEGENERATIONRESISTORS AND A UNILATERALLY CONDUCTING DEVICE CONNECTED TO A SOURCE OFREFERENCE POTENTIAL; AND MEANS INCLUDING A RESISTOR CONNECTED TO THEJUNCTION OF SAID CAPACITIVE DEVICE AND SAID UNILATERALLY CONDUCTINGDEVICE FOR FORWARD BIASING SAID UNILATERALLY CONDUCTING DEVICE WITH ASTEADY STATE BIAS CURRENT OF A MAGNITUDE SUBSTANTIALLY EQUAL TO THEMAGNITUDE OF MAXIMUM DESIRED CURRENT VARIATION THROUGH SAID TRANSISTORABOVE SAID THRESHOLD LEVEL, WHEREBY ANY SMALL AMPLITUDE INPUT SIGNALCOMPONENTS CAUSING AMPLITUDE VARIATIONS OF THE CURRENT THROUGH SAIDTRANSISTOR BELOW THE DESIRED MAXIMUM VALUE ARE AMPLIFIED AND ANY LARGEAMPLITUDE INPUT SIGNAL COMPONENTS TENDING TO CAUSE AMPLITUDE VARIATIONOF THE CURRENT THROUGH SAID TRANSISTOR ABOVE THE SAID DESIRED MAXIMUMVALUE CAUSE SAID UNILATERALLY CONDUCTING DEVICE TO BE CUT-OFF THEREBYRENDERING SAID BIASINGDEGENERATION RESISTOR OPERATIVE TO EFFECTATTENUATION OF SAID LARGE AMPLITUDE SIGNAL COMPONENTS.